Test Planning for Core-based Systems-on-chip 12+

📗 Electronic applications are currently developed underthe reuse-based paradigm. This design methodology presents several advantagesfor the reduction of the design complexity, butbrings new challenges for the test of the final circuit. In this manuscript, the main problems of the test ofcore-based systems are firstly identified andthe current solutions are discussed. Then, twopower-aware test planning approaches are proposedaiming at reducing the test costs of a core-basedsystem by means of hardware reuse and integration ofthe test planning into the design flow. The firstapproach considers systems whose cores are connectedthrough a functional bus or using a point-to-pointmodel. The second approach considers the systemsbuilt upon a network-on-chip (NoC) and proposes thereuse of the NoC infrastructure to test the embeddedcores.This book can be useful to students, researchers, DFTpractitioners, and VLSI designers that want anoverview of the testing of core-based systems andthat want to know the basics of the reuse of a network-on-chip as test access mechanism.