Energy Recovery Clocking Scheme to Achieve Ultra Low-Power

📗 As the scale of integration improves and technolgy shrinks, the more number of transistors are being packed into a chip that increases the density of the chip. This leads to the steady growth in the operating frequency and possesing capacity per chip, resulting in increased power dissipation. In modern VLSI systems, the clock is the most important signal because it controls the rate of data processing and communication. It provides a structured framework for dealing with high-complexity digital systems. Various survey and current research indicates that clock network consumes a large part of the total chip power. It is even much more than that of the ordinary logic used in the design. This book indicates the four novel low power flip-flops collectively called novel energy recovery flip-flops to reduce the power dissipation in a clock network. The energy recovery clocked flip-flops enable energy recovery from the H-tree based clock network, resulting in significant energy saving. The energy recovery flip-flops operate with a single phase sinusoidal clock generated by an efficient power clock generator.